1. Field of the Invention
The present invention generally relates to integrated circuits and fabrication of semiconductor devices. More particularly, the present invention relates to gate electrode materials in semiconductor devices.
2. Background of the Related Art
Dynamic random-access memory (DRAM) integrated circuits are commonly used for storing data in a digital computer. Currently available DRAMs may contain over 16 million cells fabricated on a single crystal silicon chip, wherein each memory cell generally comprises a single transistor connected to a miniature capacitor. In operation, each capacitor may be individually charged or discharged in order to store one bit of information. A DRAM is dynamic in the sense that charged memory cells must be refreshed or recharged periodically to maintain data integrity. Otherwise, charged memory cells may discharge through leakage to a level where they no longer appear to be set to a charged state.
A typical DRAM device generally comprises a capacitor and an access transistor. The access transistor is typically disposed above a trench capacitor to minimize the chip space occupied by the DRAM device. A trench capacitor is typically defined by a trench structure etched in the substrate. The substrate, typically doped P+ type, serves as the first electrode of the trench capacitor and is typically connected to a ground connection. The interior surfaces of the trench structure are covered by a composite dielectric film, such as a composite film of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2, which serves as the dielectric for the capacitor. The trench structure is typically filled with a heavily doped N+ polysilicon that serves as the second electrode of the capacitor. The access transistor is typically connected to the second electrode of the trench capacitor.
To facilitate construction of increasingly higher density DRAMs with correspondingly smaller-sized memory cells, capacitor structures and materials that can store the charge in smaller chip space are needed. High dielectric constant (HDC) materials (defined herein as having a dielectric constant greater than about 50) have been used successfully in such capacitor structures in many microelectronic applications, such as DRAMs. One such HDC material, Ta.sub.2 O.sub.5, has become a promising choice for the next generation of high density memory cells. Currently, the Ta.sub.2 O.sub.5 dielectric layer is deposited and then annealed to generate the desired dielectric constant. An adhesion/encapsulation layer is deposited between an electrode surface and the Ta.sub.2 O.sub.5 dielectric layer to provide better adhesion between the electrode surface and the Ta.sub.2 O.sub.2 dielectric layer during the anneal process. The adhesion/encapsulation layer also protects the Ta.sub.2 O.sub.5 dielectric layer against diffusion between the electrode surface and the Ta.sub.2 O.sub.5 dielectric layer that may cause degradation of the material properties of the device.
Titanium nitride (TiN) is currently used as the adhesion/encapsulation material for the Ta.sub.2 O.sub.5 dielectric layer. However, the use of TiN as the adhesion/encapsulation material for the Ta.sub.2 O.sub.5 dielectric layer has not completely satisfied the demands of the next generation of semiconductor devices. Silicon nitride (SiN) has also been used as a barrier, adhesion or encapsulation layer. However, the SiN barrier/adhesion/encapsulation material has similar drawbacks as the TiN material.
One particular problem is that the TiN adhesion/encapsulation material does not provide sufficient thermal performance for the anneal process required to generate higher dielectric constants (i.e., k&gt;10) from the Ta.sub.2 O.sub.5 dielectric layer. For example, the TiN adhesion/encapsulation material typically fails to protect the Ta.sub.2 O.sub.5 dielectric layer at temperatures greater than about 600.degree. C. for at least 30 seconds, which is typically required in a rapid thermal anneal process to generate higher dielectric constants from the Ta.sub.2 O.sub.5 dielectric layer. Other thermal anneal processes may even require longer processing time. Typically, at the high anneal processing temperatures, the Ta.sub.2 O.sub.5 dielectric film crystallizes and results in an increase in leakage current through the crystallized film. The increases in leakage current in the devices render the devices unstable and unacceptable for use, resulting in losses as defective devices.
Also, the TiN adhesion/encapsulation material is difficult to deposit into the small features having high aspect ratio (&gt;5:1). Typically, the TiN adhesion/encapsulation layer is deposited using reactive sputtering techniques and can achieve adequate conformal coverage for features having openings greater than about 0.3 .mu.m and aspect ratios less than about 5:1. With higher integration, the feature aperture has decreased to less than 0.25 micron while the aspect ratio of the feature may be greater than 5:1, and even greater than 10:1. It has been difficult to form thin, conformal TIN layers on the surfaces of these features. Gaps may form in the TiN adhesion/encapsulation layer, and the TiN adhesion/encapsulation layer may have uneven thickness, resulting in some regions having insufficient thickness to adequately block diffusion between adjacent layers. On the other hand, the effective dielectric property of the Ta.sub.2 O.sub.5 dielectric layer in combination with the TiN adhesion/encapsulation layer may be too low if the TiN adhesion/encapsulation layer is too thick. Thus, the difficulty in depositing thin, conformal TiN adhesion/encapsulation layers in the sub-micron high aspect ratio features has resulted in a demand for a better adhesion/encapsulation material.
Therefore, there is a need for a method for forming microelectronic devices having high dielectric constant materials. There is also a need for an adhesion/encapsulation material useful as a gate electrode liner for the next generation of sub-micron high aspect ratio microelectronic devices. Particularly, there is a need for an adhesion/encapsulation material that is useful for forming devices in sub-micron, high aspect ratio features and can withstand high temperatures during processing, particularly during annealing treatments of the devices.